ESD protection has been a main concern in the reliability of integrated circuit (IC) products in submicron complimentary metal-oxide-silicon (CMOS) technologies. For example, gates in N-type metal metal-oxide-silicon (NMOS) and P-type metal-oxide-silicon (PMOS) transistors in input buffers of a CMOS IC are often directly connected to input pads of the IC, causing the CMOS input buffers to be vulnerable to ESD damage. Large ESD devices are used to protect the gates of a CMOS input buffer, but the large ESD devices add significant capacitance to the input pins, and this slows down the input signal propagation. This is not tolerable for high-speed input functions, such as high-speed clock inputs. Therefore, efforts have been made to design ESD protection structures in the input circuitry of an IC that offer sufficient ESD protection while adding as little capacitance to the IC input pins as possible.
Grounded gate NMOS transistors are a frequent choice for an ESD protection circuit. Such a device operates to provide ESD protection by triggering a parasitic lateral bipolar transistor inherent in the MOS structure where the source and drain regions of the MOS transistor constitute the emitter and collector of the lateral bipolar transistor and the substrate constitutes the base. See, for example, A. Amerasekera et al., ESD in Silicon Integrated Circuits, pp. 81-95 (2d Ed., Wiley, 2002).
FIG. 1 depicts a cross-section of such a conventional NMOS transistor 10. The transistor comprises a P-type substrate 20, or a P-type well in a substrate, in which are formed first and second N-type lightly doped drain (LDD) regions 30, 35, an N-type source region 40 and an N-type drain region 45. An insulating layer 50 is located on the substrate and a gate 60 is on the insulating layer between the LDD regions. Typically, the gate is used to mask the portion of the substrate underneath the gate during the formation of the LDD regions, the source and the drain. Source region 40 is connected to ground and drain region 45 is connected to an input/output (I/O) pad that is to be protected against ESD.
P-type substrate 20 and N-type source region 40 form a first P-N junction 70 and P-type substrate 20 and N-type drain region 45 form a second P-N junction 75. As a result, a parasitic lateral bipolar transistor 80 is present in transistor 10 having a base-emitter junction that is the first P-N junction 70 and a base-collector junction that is the second P-N junction 75. In the event of a positive voltage ESD event on the input pad, the drain junction is driven into breakdown and avalanche and the parasitic transistor is triggered into conduction to discharge the ESD pulse.
One problem with a grounded-gate NMOS transistor is large capacitance between its drain and ground due to large transistor size. A common practice to reduce the capacitance is to insert some series diodes 212, 214 between an input pad and the drain of an NMOS transistor 10 as shown in FIG. 2. NMOS transistor 10 is the same as transistor 10 of FIG. 1. During the ESD discharge, the ESD current flows through the diodes and causes avalanching in the drain junction 75 of the NMOS transistor. However, since the triggering of the parasitic transistor relies on passing current through the series diodes and the junction breakdown of the NMOS transistor, the triggering tends to be slow and non-uniform and requires relatively high voltages. For example, at 2 Amperes of ESD current, each diode can have a voltage drop of 1.5V. Thus, the trigger voltage is increased by at least 1.5V depending on the number of diodes put in series. High voltages, however, are not desirable with modern MOS transistors because they have extremely thin gate oxides that are vulnerable to rupture. In addition, since the triggering of such a transistor relies on junction breakdown, the triggering tends to be non-uniform over a large structure. This, when combined with the higher trigger voltage introduced by the series diodes, makes ESD protection ineffective.